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Eab User Accusing AC Team of Stealing IPpage  1 2 3 4 

David Wright

Posts 363
05 Jun 2020 14:54


The discontents have an avenue for their bitterness. Just join the riots in your nearest city if you haven't already.


Otto PS
(Needs Verification)
Posts 26/ 1
05 Jun 2020 15:22


haha, this looks like a bag full of fighting cats, I have not seen anything like this in other developments of 68k accelerators. I love the apollo team, they not only gave me a good accelerator, they also provide me with poison and gossip!


Michal Pietal

Posts 223
05 Jun 2020 22:17


See?  Told ya the IP matters, but instead, you called me a wannabe-lawyer.

How can you possibly know I am not into law by the way??

Renaud it is up to the Team though, as stated in another thread.  Either you help sorting IP things out (or at least, help clarify what's black, what's white and what's in between), or be damned, numerously, by some IP rookies' posts anywhere, for ages!!


Adam A

Posts 122
05 Jun 2020 22:44


@Michal Pietal

Imho, I think the best for the apollo team is to totally ignore it. your solution could make things worse. These sort of things has always been happening in the amiga scene. nothing will change.

and legalwise, there is no proof. so they shouldn't even bother to reply.



Gunnar von Boehn
(Apollo Team Member)
Posts 5296
06 Jun 2020 06:35


Clearly the person writing the post, showed a major lack of technical understanding and sadly no clue about Coldfire CPUs.
 
 
Everyone knowing the Coldfire architecture will know that:
 
The design goal of the Coldfire V1 is to be as small and as lowest cost as possible. Its designed to replace 8Bit controllers.
The V1 was never designed to be capable or fast.
Coldfire V1 is internally very simple and tuned for lowest possible production cost. Therefore the structure of the V1 can never be used as basis for a well performing CPU.
 
From Coldfire several different generation were designed over the years V1,V2,V3,V4,V4e.
The design goal slightly changed over the generations and the V4 and V4e were designed for more performance.

Actually also a V5 Coldfire was designed and a V6 planned.
But Motorola already decided to give up on the Coldfire line at this time and the V5 was is only provided to one special customer (HP).
 
 
A couple years ago we did an very extensive comparison between Coldfire V4e and Apollo 68080 CPU.
And also ran many benchmarks on both.
The V4e is the best available Coldfire on the market (as Motorola not sells the V5 publicly).

As you might know the Apollo 68080 does beat the Coldfire V4e in each and every benchmark by far - assuming same clock.
 
You might have seen several charts on our website showing
how the Apollo reaches in a number of benchmarks over 5 times the speed of the Coldfire V4.
 
 
As long time CPU architects we of course know - how the different CPUs on the market are constructed.
We know very well how each Motorola model is internationally structured. We know very much how the CPUs work.
We know the tricks that AMD and INTEL cores use.
We we know SUN, ARM, and VIA.
 
The same way as every top sportsman will compare himself with the others. And how the top tennis player will know very well where the strength and weaknesses of the other top player are - we also know  very well what strength and weaknesses our competition have.
 
But one thing is clear:
 
The Coldfire V1 is totally below our league.
Comparing a Coldfire V1 to the Apollo 68080  is like comparing a FIAT UNO to a McLaren Mercedes Formula1 Race Car.
Yes both have 4 wheels and a composition engine. :-)
 
 
Now how serious would you take someone claiming Mercedes did build their Formula 1 winning car on stolen blue prints of a Fiat Uno?

If you compare APOLLO 68080 with Coldfire then Apollo is the most similar to the V6 Coldfire which only was planned but never build.
Both designs are aimed for maximum performance.

If you are not afraid of deep technical details and want to know more then we can explain how these different cores internally works.



A1200 Coder

Posts 71
06 Jun 2020 07:42


Interesting. Can you tell us then which CPU architecture your design is based on? The 68080 seems to have a 68040 stack frame, or Sysinfo originally identified the 68080 as a 68040.I can also tell that you didn't use the 68060 as a starting point, as some instructions are still faster on the 68060 (overall the 68080 is still faster than the 68060, as it has many improvements that the 68060 doesn't have).


Master APEX

Posts 37
06 Jun 2020 12:05


DamianDs crazy vendetta will hopefully not destroy the EAB culture.
I am already on his list. :-)


Markus B

Posts 207
06 Jun 2020 15:22


I don't get how such people can keep their moderator role.


Gunnar von Boehn
(Apollo Team Member)
Posts 5296
06 Jun 2020 15:35


A1200 coder wrote:

Interesting. Can you tell us then which CPU architecture your design is based on? The 68080 seems to have a 68040 stack frame, or Sysinfo originally identified the 68080 as a 68040.

...
Well this needs a much longer explanation.

A1200 coder wrote:

I can also tell that you didn't use the 68060 as a starting point, as some instructions are still faster on the 68060

No CPU instructions is faster on 060 than on 080.

When you look at CPU design there are many items you can looks at

a) vertical or horizontal pipeline?
b) number of pipelines stages
c) bandwidth of Icache in bits/byte
d) maximum number of Instructions decoded per cycle
e) Number of EA units
f) DCache access width in bits
g) Number of DCache access per cycle
h) DCache access latency
i) Dcache features like Prefetch or Streaming
j) number of ALU units, special Units
k) Branch prediction

 



Don Adan

Posts 33
06 Jun 2020 20:45


Gunnar von Boehn wrote:

A1200 coder wrote:

  Interesting. Can you tell us then which CPU architecture your design is based on? The 68080 seems to have a 68040 stack frame, or Sysinfo originally identified the 68080 as a 68040.
 

 
  ...
  Well this needs a much longer explanation.
 
 
A1200 coder wrote:

  I can also tell that you didn't use the 68060 as a starting point, as some instructions are still faster on the 68060
 

  No CPU instructions is faster on 060 than on 080.
 
 
 
 
  When you look at CPU design there are many items you can looks at
 
  a) vertical or horizontal pipeline?
  b) number of pipelines stages
  c) bandwidth of Icache in bits/byte
  d) maximum number of Instructions decoded per cycle
  e) Number of EA units
  f) DCache access width in bits
  g) Number of DCache access per cycle
  h) DCache access latency
  i) Dcache features like Prefetch or Streaming
  j) number of ALU units, special Units
  k) Branch prediction
 
 
 

Minimum one 68060 CPU instruction is fastest. 32 bit mulu.l, 2 cycles on 68060, 3 cycles on 68080.


Gunnar von Boehn
(Apollo Team Member)
Posts 5296
07 Jun 2020 08:22


Don Adan wrote:

Minimum one 68060 CPU instruction is fastest.
32 bit mulu.l, 2 cycles on 68060, 3 cycles on 68080.

As you correctly stated the default build setting for the 68080 is 3 cycle as this allows increases the total CPU clockrate.
But on 68080 you can configure and choose whether you prefer this instruction can finish in either  2 cycle or 3 cycles.
 



Gernt Gerloff

Posts 49
07 Jun 2020 08:39


I don't think this eab thread has any point there.
It shows no evidence, not even something one could follow to find evidences, for me it reads certainly like FUD.
All this talking about magically appearing of implementation, but forgets to mention the years between the events.
And looking at the links, they are not really explain anything related to the case. It only shows that Gunnar certainly already worked a while on 68k cpu, so has the knowledge to do such implementation.
A prove would be an error (or unusual behavior) in the original FPGA implementation which is still there in 68080, otherwise that's a very weak (close to non-existing) case.


Gunnar von Boehn
(Apollo Team Member)
Posts 5296
07 Jun 2020 09:32


Gernt Gerloff wrote:

  I don't think this eab thread has any point there.
 

Its based on technical nonsense.

A) reverse engineering a FPGA load is not possible

B) Even if someone could do this.
This would only give you a netlist=floorplan but would not give you the source. This mean you can never alter or improve it.
Every with some FPGA clue knows this.
C) The Coldfire V1 is very low performing CPU.
Turning this into something as fast as the 68080 would be a major miracle. Compared to this turning water to wine is nothing.

The whole thread displays lack of clue about CPUs and FPGA.

 
 
 
 
 
 
 
 
 


Ray Couzens

Posts 91
07 Jun 2020 11:37


It's probably best to just ignore it, let them have fun with their
conspiracy theories, many people love these things, and just move on.  Not worth the time to worry about.


Otto PS
(Needs Verification)
Posts 26/ 1
07 Jun 2020 20:28


This is great fun, but it is a futile discussion. In case the apollo team has taken another IP core as a base, I doubt that a part of it has remained usable in the current implementation 68080.


Manuel Jesus

Posts 151
09 Jun 2020 02:04


To chime in here in regards to NonAr... Before joining the team I did see a conversation on social media where she and others were openly discussing reversing Vampire cards and the FPGA core. Imagine my surprise when she showed up in core channel.

I let the team know and after all this time this drama surfaces.


Saladriel Amrael

Posts 157
09 Jun 2020 11:24


Olaf Schoenweiss wrote:

sad... if I look at other retro communities (like C64) I never see such drama

Well, ZX Spectrum community was overwhelmingly enthusiast about the Spectrum Next (Literally, Spectrum's Vampire Standalone equivalent).
It's a real Pity that Amiga community is more divided and not as unite


Nixus Minimax

Posts 416
09 Jun 2020 13:19


Gunnar von Boehn wrote:

 
  A) reverse engineering a FPGA load is not possible
 
  B) Even if someone could do this.

If some could do this, they are probably skilled enough to create their own ColdFire implementation in less time than reversing it from a netlist! Another logic flaw of the allegation is that it makes perfect sense to start with a ColdFire implementation if you want to create your own 68k because the ColdFire ISA is (at least) an order of magnitude less complex than full 68k. Then the argument about the hardware FPU coming out of thin air shows that she didn't even pay attention while she was on the team. The hardware FPU was completed years ago (and not done by Gunnar) but not debugged. FEMU gave a very useful tool for debugging the FPU because it allowed enabling single instructions in hardware and checking whether programs started behaving differently.



Ron Valen
(Needs Verification)
Posts 12/ 2
04 Oct 2020 16:07


Nonarkitten is not offering Vampire 1200 V2 like products for sale.
 
I'm not going to pay crazy 68060 Rev 6 + accelerator card prices.
 

ColdFire v1 claim was LOL

It's like claiming 8086 microarchitecture = Pentium Pro.


Stefano Briccolani

Posts 563
04 Oct 2020 17:20


Same shit by same people. They're scared to death by vampire

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