**Operation:** Source * Destination -->; Destination

**Assembler Syntax:**

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MULU.W <ea>, Dn` `

` `

16 x 16 -->; 32

` `

MULU.L <ea>, Dl` `

` `

32 x 32 -->; 32

` `

MULU.L <ea>, Dh:Dl` `

32 x 32 -->; 64

**Attributes:** Size = (Word, Long)

**Description:** Multiplies two unsigned operands yielding an

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unsigned result. This instruction has a word operand form

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and a long-word operand form.

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In the word form, the multiplier and multiplicand are

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both word operands, and the result is a long-word operand.

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A register operand is the low-order word; the upper word

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of the register is ignored. All 32 bits of the product are

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saved in the destination data register.

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In the long form, the multiplier and multiplicand are both

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long-word operands, and the result is either a long word or

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a quad word. The long-word result is the low-order 32

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bits of the quad word result; the high-order 32 bits of the

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product are discarded.

**Condition Codes:**

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X Not affected.

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N Set if the result is negative. Cleared otherwise.

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Z Set if the result is zero. Cleared otherwise.

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V Set if overflow. Cleared otherwise.

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C Always cleared.

Note: Overflow (V = 1) can occur only when multiplying 32-bit

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operands to yield a 32-bit result. Overflow occurs if the

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high-order 32 bits of the quad-word product are not the

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sign extension of the low-order 32 bits.