CAS2 Destination 1 -- Compare 1 -->; cc;
if Z, Destination 2 -- Compare 2 -->; cc
if Z, Update 1 -->; Destination 1; Update 2 -->; Destination 2
else Destination 1 -->; Compare 1; Destination 2 -->; Compare 2
CAS2 Dc1:Dc2, Du1:Du2, (Rn1):(Rn2)
Attributes: Size = (Word, Long)
Description: CAS2 compares memory operand 1 (Rn1) to
compare operand 1 (Dc1). If the operands are equal, the
instruction compares memory operand 2 (Rn2) to compare
operand 2 (Dc2). If these operands are also equal, the inst-
ruction writes the update operands (Du1 and Du2) to the
memory operands (Rn1 and Rn2). If either comparison fails,
the instruction writes the memory operands (Rn1 and Rn2)
to the compare operands (Dc1 and Dc2). The instruction
accesses memory using locked or read-modify-write transfer
sequences. This provides a means of synchronizing several
X Not affected.
N Set if the result is negative. Cleared otherwise.
Z Set if the result is zero. Cleared otherwise.
V Set if an overflow is generated. Cleared otherwise.
C Set if a borrow is generated. Cleared otherwise.
The CAS and CAS2 instructions can be used to perform secure
update operations on system control data structures in
a multiprocessing environment.
In the MC68040 if the operands are not equal, the destination 1
operand is written back to memory to complete the locked