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BFINS Instruction Bug?

Adam Polkosnik

Posts 29
15 Jul 2019 22:05

I think that some of the graphical glitches are caused by buggy implementation of BFINS in tg68. It's shared between MIST, MISTer, and the Vampire Gold 3 Alpha. It manifests itself in Goraud Pulse part of Nexus7 demo
E.g. BFINS D3,($7000,A1){D4:D2}.

Andrew Copland

Posts 113
16 Jul 2019 11:42

It should be fairly easy to write some unit tests for that to prove the theory

Adam Polkosnik

Posts 29
21 Jul 2019 05:30

It turns out that it's triggered by access to non-aligned memory. E.g. BTST #0,$dff005 or BTST #0,($5,A6)

Philippe Flype
(Apollo Team Member)
Posts 281
21 Jul 2019 07:53

I'm trying locate this since some days.

And indeed i didnt find any Nexus7 BF issues.

I see very well where is the Gouraud routine.

But cant catch an error.


Also i tested a bunch of unaligned BTST, also without issues.

Do you have precise stuff to show me, any more hints please ?

For information, the 080 BF set is own implementation, not tg68 based.

Adam Polkosnik

Posts 29
21 Jul 2019 13:57

I've tracked it down to be an unalligned access to the custom chip memory. Basically, I kept freezing the demo at varying instruction counts from the last "restore point" narrowing it down to the spot where the display was getting corrupted. See the MiSTer issue. BFINS implementation is just fine (I've even built and flashed a minimum with a slightly altered code for BFINS to test my initial theory), it's just BTST that reads from $dff005 causes mayhem.
  On my a500 V2+, I only had a WHDLOAD version of the demo, and it was giving me the corrupted torus on the Gold 3 alpha. Check out the  other AGA demo mentioned towards the end of that MiSTer issue, I didn't check that one on Gold 3, since I loaded the latest beta of 2.12. *UAE seems to have fixed the unalligned memory access long time ago a I pointed out in the issue.
  I'm planning on building a fix for MiSTer once I figure out tg68k some more.

Gunnar von Boehn
(Apollo Team Member)
Posts 4796
22 Jul 2019 06:48

Adam Polkosnik wrote:

it's just BTST that reads from $dff005 causes mayhem.

There is nothing wrong with the BTST on $DFF005.
You just wild guessing.

Adam Polkosnik

Posts 29
22 Jul 2019 08:21

Well, yeah I'm throwing stuff around and then testing if it sticks. When I step through it in the debugger, the 7th bitplane gets corrupted. I've patched the wait vb piece to use an aligned read, and it happened too. At this point my next wild guess is either chipset issue or some weird stuff is happening in the vertical blank interrupt. Nobody managed to get it fixed for quite a while and I'm just bouncing between UAE and MiSTer, at least I have some fun with HRTMon.

Adam Polkosnik

Posts 29
17 Oct 2019 08:28

Ok, so my initial guess turned out to be pretty close.
I managed to fix it on Mister. Basically, there are some bits that sometimes are used for switching between Address registers and Data registers, but in case of some instructions, these bits are not used, because the instructions only support Data registers and so on.
This is how I fixed it on MiSTer.

Andrew Copland

Posts 113
22 Oct 2019 11:47

Nice work Adam!

posts 9