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Documentation about the Vampire hardware

VASM / 68080 Snippetspage  1 2 

Tommo Noorduin

Posts 132
16 Apr 2022 13:25


; another snippet

; 64 bit logic
; (debugger shows only the lower 32 of the 64 bits.)

  load.w #$00ff,d0 ; result d0=00ff00ff
  move.l #$0ff00f0f,d1 ; result d1=0ff00f0f

  pand d0,d1,d2  ; result d2=00f0000f
  por d0,d1,d3  ; result d3=0fff0fff
  peor d0,d1,d4  ; result d4=0f0f0ff0
  pandn d0,d1,d5  ; result d5=0f000f00




Tommo Noorduin

Posts 132
19 Apr 2022 10:22


; another snippet

; bit select.
; if a mask bit is set the source bit is taken
; else no change

; bsel is also a 64 bit instruction.

  move.l #$12345678,d0
  move.l #$0000ffff,d1 ; mask
  move.l #$87654321,d2
  bsel d0,d1,d2  ; result d2=87655678
  move.l #$f0f0000f,d3 ; mask
  move.l #$87654321,d4
  bsel d0,d3,d4  ; result d4=17354328

  move.l #$87654321,d5
  bsel d0,d5,d5  ; result d5=02244220

  move.l #$87654321,d6
  pand d0,d6,d7  ; result d7=02244220



Tommo Noorduin

Posts 132
20 Apr 2022 20:31


; psub is identical to padd, so:
; 4x sub.w = psubw d0,d1,d2
; 4x sub.w unsigned & saturated(limited)
; = psubusw d0,d1,d2
 
; 8x sub.b = psubb d0,d1,d2
; 8x sub.b unsigned & saturated(limited)
; = psubusb d0,d1,d2

; butterfly = add & sub combined.

  move.l #$01038081,d0
  move.l #$44028183,d1

; 4x add.w & 4x sub.w

  bflyw d0,d1,d2  ;result in d2 & d3
  ; result d2 = 45050204 ; d2 = d1 + d0
  ; result d3 = 42ff0102 ; d3 = d1 - d0
  ; d2 can be changed to any EVEN data-register

; 8x add.b & 8x sub.b

  bflyb d0,d1,d4
  ; result d4 = 45050104 ; d4 = d1 + d0
  ; result d5 = 43ff0102 ; d5 = d1 - d0



Tommo Noorduin

Posts 132
21 Apr 2022 16:28


; back to storem3, because i read that sonic ( EXTERNAL LINK ) uses it.

; storem3 seem to ignore the content of the second argument,
; and uses the argument-number as value.

  load.q #$123456789abcdef0,d0 ; source
  lea val0,a0

  storem3 d0,d0,(a0)+ ; result val0 = 000000009abcdef0
  storem3 d0,d1,(a0)+ ; result val1 = 123456789abcdef0
  storem3 d0,d2,(a0)+ ; result val2 = 123456789abcdef0
  storem3 d0,d3,(a0)+ ; result val3 = 1234567800000000
  storem3 d0,d4,(a0)+ ; result val4 = 000000009abcdef0
  storem3 d0,d5,(a0)+ ; result val5 = 123456789abcdef0
  storem3 d0,d6,(a0)+ ; result val6 = 123456789abcdef0
  storem3 d0,d7,(a0)+ ; result val7 = 1234567800000000

; d0 & d4 write only the low-32 bits.
; d3 & d7 write only the hi-32 bits.
; d1,d2,d5,d6 write full 64 bits, like normal store would do.

  illegal

  DATA

val0 ds.l 2
val1 ds.l 2
val2 ds.l 2
val3 ds.l 2
val4 ds.l 2
val5 ds.l 2
val6 ds.l 2
val7 ds.l 2
 


Tommo Noorduin

Posts 132
22 Apr 2022 13:55


; blitter logic: minterm

  move.l #$11110000,d0
  move.l #$11001100,d1
  move.l #$10101010,d2

; logic operation
  move.b #%11100010,d3 ; result d3 = 000000e2
; this would be d1 as mask selecting d0, otherwise d2

  minterm d0-d3,d4  ; result d4 = 11100010

; powerfull logic operation!
; any locical bit function can be made in d4 for
; the 3 64_bit inputs.

; Other logic_op, set bit if only 1 of the 3 inputs is set
  move.b #%00010110,d3 ; result d3 = 00000016

  minterm d0-d3,d6  ; result d6 =00010110
  move.l d6,d5

; same logic, new inputs:
  move.l #$01234567,d0
  move.l #$11002266,d1
  move.l #$f0f000ff,d2

  minterm d0-d3,d6  ; result d6 =e0d36798

; note:
; source is 4 following data-registers, where the first one is modulo 4
; destination is EVEN data-register.



Tommo Noorduin

Posts 132
23 Apr 2022 19:04


; a tool

; The last value written to chip-registers can be read.
; by using dfe000

  move.l $dfe080,a0 ;copper list 1 pointer, a0 =000055b8
  move.l $dfe084,a1 ;copper list 2 pointer, a1 =00005630

  move.w $dff002,d0 ;dma con read, dmacon = 03f0
  move.w $dfe002,d1 ;d1 = 0000: last value written to this read-only address
  ; is zero because there has been no writting to that location.

  move.w $dfe096,d2 ;dma con, d2 = 8180
  ; so the last action was: set bitplane & copper


Tommo Noorduin

Posts 132
24 Apr 2022 10:55


; Another 4 register input instruction:

  load.q #$1122334455667788,d0
  load.q #$99aabbccddeeff00,d1
  load.q #$123456789abcdef0,d2
  load.q #$1111111111111111,d3

  transhi d0-d3,d4:d5
  ; result d4 = (112299aa)12341111
  ; result d5 = (3344bbcc)56781111

  translo d0-d3,d6:d7
  ; result d6 = (5566ddee)9abc1111
  ; result d7 = (7788ff00)def01111

  illegal

; A bit like c2p
; C2P does transpose 8x8 bits
; TRANS does transpose 4x4 words
 
; Same restrictions as minterm:
; source is 4 following data-registers, where the first one is modulo 4
; destination pair, the first must be EVEN data-register.



Tommo Noorduin

Posts 132
25 Apr 2022 14:44


; 4 x word multiply in 3 variations
; hi part, low part & middle part

  move.l #$12345678,d0
  move.l #$02018010,d1

;1234 x 0201 = 00247a34
;5678 x 8010 = d4c96780

  pmulh d0,d1,d2  ;result d2 = 0024d4c9
  pmul88 d0,d1,d3  ;result d3 = 247ac967
  pmull d0,d1,d4  ;result d4 = 7a346780


Tommo Noorduin

Posts 132
26 Apr 2022 19:00


; another snippet

; convert 2 x 4 signed words to 8 unsigned bytes

  load.q #$008012340044fffd,d1
  packuswb d0,d1,d2  ;result d2 = 80ff4400



Tommo Noorduin

Posts 132
27 Apr 2022 17:55


Completly unrelated image:

; mini & maxi

  move.l #$123460cd,d0
  move.l #$4321ab70,d1

; unsigned byte

  pminub d0,d1,d2  ;result d2 = 12216070
  pmaxub d0,d1,d3  ;result d3 = 4334abcd

; signed
  pminsb d0,d1,d4  ;result d4 = 1221abcd
  pmaxsb d0,d1,d5  ;result d5 = 43346070

; unsigned word

  pminuw d0,d1,d2  ;result d2 = 123460cd
  pmaxuw d0,d1,d3  ;result d3 = 4321ab70

; signed
  pminsw d0,d1,d4  ;result d4 = 1234ab70
  pmaxsw d0,d1,d5  ;result d5 = 432160cd




António Orlando

Posts 7
28 Apr 2022 08:45


Tommo Noorduin wrote:

  ; back to storem3, because i read that sonic ( EXTERNAL LINK ) uses it.
 
  ; storem3 seem to ignore the content of the second argument,
  ; and uses the argument-number as value.
 
 
    load.q #$123456789abcdef0,d0 ; source
    lea val0,a0
 
    storem3 d0,d0,(a0)+ ; result val0 = 000000009abcdef0
    storem3 d0,d1,(a0)+ ; result val1 = 123456789abcdef0
    storem3 d0,d2,(a0)+ ; result val2 = 123456789abcdef0
    storem3 d0,d3,(a0)+ ; result val3 = 1234567800000000
    storem3 d0,d4,(a0)+ ; result val4 = 000000009abcdef0
    storem3 d0,d5,(a0)+ ; result val5 = 123456789abcdef0
    storem3 d0,d6,(a0)+ ; result val6 = 123456789abcdef0
    storem3 d0,d7,(a0)+ ; result val7 = 1234567800000000
 
  ; d0 & d4 write only the low-32 bits.
  ; d3 & d7 write only the hi-32 bits.
  ; d1,d2,d5,d6 write full 64 bits, like normal store would do.
 
    illegal
 
    DATA
 
  val0 ds.l 2
  val1 ds.l 2
  val2 ds.l 2
  val3 ds.l 2
  val4 ds.l 2
  val5 ds.l 2
  val6 ds.l 2
  val7 ds.l 2
   
 

 
  Hi Tommo.
 
  Isn't the mask read from the contents of Dn?
  It would justify this
 
      storem3 d0,d0,(a0)+ ; result val0 = 000000009abcdef0
 
  because in the documentation it says
 
      d[0] = ( m & (1<<(7-i)) ) ? a[0] : d[0];
 
  Since bit 7 is 1, you get the 0xf0 as the lowest byte in val0.
  Mask 0xf0 means that you'll get the lower 4 bytes from d0 and the rest from val0.
  Mask 0x0f would be the opposite i.e. 1234567800000000.
 
  The other results (for d1,d2,d3,d4,etc.) really depend on the value stored at each register.
 
  Please also note that the Mask field in extension word 1 (bits 8-11)  and the corresponding extension bit in word 0 (bit 6) would not be enough to filter the 8 possible bytes in a qword. So it makes sense that the mask is obtained from a data register.
 
  At least this is how I interpret the little information/documentation that we have available.
 
  Cheers
  aorlando
 


Tommo Noorduin

Posts 132
28 Apr 2022 17:45


more STOREM3

Hi António,

Before your post i was aware storem3 is more complex.
I was thinking something like:

  Store bytes from source to destination, depending on mode
  0: 2x 32bit color when msb=1
  1: 2x 32bit color when msb=1 (but only when individual R,G,B>0)
  2: src
  3: 4x 15bit color when msb=0

But i am in the dark here.
I am trying to gain knowledge of the new 68080 stuff, just like you.

António Orlando wrote:

  At least this is how I interpret the little information/documentation that we have available.

That is why my guessing on storem3. looking at how it behaves.

d[0] = ( m & (1<<(7-i)) ) ? a[0] : d[0];  is probably for storem only.

If you have/see documentation of storem3 i would apreciate that!
Well actually anything about special 68080 instructions is good.
Just post links here!

I hope to contribute a bit by showing some examples.

The snippets are for everyone to see what it does.
They can copy it and use it in the debugger from devpac,
so they can even do the steps themself to see what it does inside the CPU.

Thank you for you post, nice to know you are also looking at the powerfull possibilities the 68080 has.



Gunnar von Boehn
(Apollo Team Member)
Posts 6207
29 Apr 2022 06:37


Tommo Noorduin wrote:

If you have/see documentation of storem3 i would apreciate that!

Store3M does write 8 Byte in 1 instruction.
The write enables are depending on content of the data.
This means only non transparent pixels are written.
This makes STORE3M optimal for Soft Sprites.

STORE3M supports 8bit, 16bit, 15bit, and 32bit pixels


Tommo Noorduin

Posts 132
29 Apr 2022 08:45


Gunnar wrote:

  STORE3M supports 8bit, 16bit, 15bit, and 32bit pixels

Ahh, good.
So the Question becomes:
- How -

locic points me to
8bit & 16bit : 0 or else
15bit : msb is used
32bit : msb or byte is used

Need to test that.
so STORE3 story is
... to be continued.


Tommo Noorduin

Posts 132
29 Apr 2022 09:11


; ammx does not set the status register.
; vector compare
; 8 bytes or 4 words

  clr.l d0
  move.l #$01ff0083,d1

  pcmpeqb d0,d1,d2 ;result d2 = 0000ff00 , selected zero
  pcmphib d0,d1,d3 ;result d3 = ffff00ff , selected unsigned hi/greater
  pcmpgtb d0,d1,d4 ;result d4 = ff000000 , selected signed hi/greater
  pcmpgeb d0,d1,d5 ;result d5 = ff00ff00 , selected signed greater or equal

  ; pcmpgeb.q #0,d1,d5 ;same but a (4+8)byte instruction size
  ; pcmpgeb.w #0,d1,d5 ;same but a (4+2)byte instruction size

; signed less than , from d1
  pandn d5,d1,d6 ;result d6 = 00ff0083

; unsigned less than or equal , from d1
  pandn d3,d1,d7 ;result d7 = 00000000

; note:
; only eq/hi/gt/ge are valid conditions




António Orlando

Posts 7
29 Apr 2022 09:13


Hi Tommo.
   
   
Tommo Noorduin wrote:

    If you have/see documentation of storem3 i would apreciate that!
   

   
    I'm very sorry but I did confuse storem with storem3 ;(
   
    Looking at your asm code, and considering the documentation and what Gunnar just mentioned, it seems that for
   
        storem3 A,M,D
   
    when M = 0
        copy only bytes where (A & 0x80) != 0
        (this is the only way we can explain your result i.e. use A instead of D)
   
    when M = 1
        copy only words where D != 0xF81F
   
    when M = 2
        copy only words where (D & 0x8000) == 0
   
    when M = 3 (
        copy only longs where (D & 0x80000000) == 0
   
    It would be easy to check this by executing the instructions with specially crafted arguments.
    For mode 0 I would use
   
        d0 = $8102830485068708 => val0 $8100830085008700
   
    For mode 1 I would use
     
        d0 = $1122334455667788, val1 = $f81f0000f81f0000 => val1 = $1122000055660000
     
    For mode 2 I would use
     
        d0 = $1122334455667788, val1 = $8123012381230123 => val1 = $8123334481237788
   
    For mode 3 I would use
     
        d0 = $1122334455667788, val1 = $8123012301234567 => val1 = $8123012355667788
   
   
Tommo Noorduin wrote:

    I hope to contribute a bit by showing some examples.
   

   
    Thanks a lot for that, an also for the 680x0_instruction_set.ods file which helped me clarify some stuff.
   
   
Tommo Noorduin wrote:

    Thank you for you post, nice to know you are also looking at the powerfull possibilities the 68080 has.
   

   
    I hope I can finish my "m68k" tool in the next week or two, and then I can share it with every body.
    It will give you the possibility of assembling any instructions using the command line, so it would be helpful to encode "touch (a0)" for example.
    Unfortunately I'm struggling a little bit to find the information needed to make a complete disasm/asm engine.
    But it's better to have something to start with, than nothing at all.
    Cheers
    António
 
  PS: here is an example using my own syntax
 
  #0x000a1c94: storem3 %r(d5), %ib(0x02), %m([b5,-0x2710],a2.w*2,0x000f4240)
  ff 35 52 26 a3 27 d8 f0 00 0f 42 40
                    2:bdw
                          2:odl
   


Tommo Noorduin

Posts 132
29 Apr 2022 19:48


António wrote:

    I hope I can finish my "m68k" tool...

Hi António,
More tools = better!
 
Figured it out,
here a slightly bigger snippet (Hehehe..)
 

 
  - Will we ever tame this wild '68080' beast ? -
 
In the purple rainy sky we see:
The instruction formerly known as Pixel-merge.
 
  ...
 
STOREM3 again.
  - For fast chunky cpu sprites -
 
mode 0,1,2,3 is identical to 4,5,6,7 so modulo 4
 
    0: 2x long, mask msb=1 , 32bit chunky
    1: 8x byte, mask byte<>0 , 8bit indexed
    2: src
    3: 4x word, mask msb=0 , 15bit chunky
 
; code snippet:
 
    lea pix,a0
    load.q #$800001230100ab00,d0
    storem3 d0,d0,(a0)+ ; result = 80000123 44444444
    storem3 d0,d1,(a0)+ ; result = 80440123 0144ab44
    storem3 d0,d2,(a0)+ ; result = 80000123 0100ab00
    storem3 d0,d3,(a0)+ ; result = 44440123 01004444
    storem3 d0,d4,(a0)+ ; result = 80000123 44444444
    illegal
 
    DATA
pix
    REPT 5
    dc.l $44444444,$44444444
    ENDR
 
; end code
 
Notes:
VASM needs registers, and the second operand is immediate.
so encode storem3 d0,#1,d2 as storem3 d0,d1,d2
 
(No bug)
 
A possible mode 2 future upgrade could be:
16bit and test on zero.



Tommo Noorduin

Posts 132
30 Apr 2022 18:59


; average

  move.l #$0123fe01,d0
  move.l #$0424fd70,d1

  pavgb d0,d1,d2 ;result d2 = 0324fe39

; note:
; unsigned rounded up
; pavgw d0,d1,d2 not exist



Tommo Noorduin

Posts 132
01 May 2022 09:39



Note:
  There is mention of:
  pabsb, pabsw, touch, pixmrg & tex in connection to ammx.

  The first three i can not explane the current behavior.
  pixmrg might be storem3.
  tex8/16/24 is not in vasm yet, but i can give the working of it.
  Just make a request. It has to be in opcodes (dc.w).

.

Okay,
  One more TRANS, music this time.

  With a nice platonic solid, an icosahedron.

  With 7 hexagons as segmented lines connecting the pentagons.
  And every triange it makes filled with more hexagons.

  -= For anyone who wants to try that be aware: =-

face=6+5+4+3+2+1=7*3=21 hexagons
20 faces = 21*20=420 hexagons
30 edges = 7*30=210 hexagons
12 vertices= 12 pentagons
total hexagons = 630

hexigon
8 faces  5040
18 edges 11340
12 verticles 7560

pentagon
7 faces 784
15 edges 180
10 verticles 120

total
faces 5824
edges 11520
verticles 7680


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