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| | Martin White
Posts 85 27 Dec 2019 16:22
| Can someone confirm please. The picture here clearly shows pin 1 as the top left pin of the JTag port: EXTERNAL LINK But the PCB mask has pin 1 marked as the bottom left of the 10 pins. Before I guess and destroy my board, could someone tell me which is correct please? Thanks.
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| | Martin White
Posts 85 27 Dec 2019 19:00
| Looked up the pin out and worked it out. It seems the image on the wiki is wrong and the pcb screen is correct. Which is actually reassuring!
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| | Neil Shacklady
Posts 29 28 Dec 2019 15:07
| Hi Martin - are you flashing a new core to your V4SA? If so could you let me know how you get on? I'll have to wait for them to be released as exe files.
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| | Vojin Vidanovic (Needs Verification) Posts 1916/ 1 28 Dec 2019 17:05
| Neil Shacklady wrote:
| Hi Martin - are you flashing a new core to your V4SA? If so could you let me know how you get on? I'll have to wait for them to be released as exe files.
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On Slack / IRC but they are heavy beta. There will be .exe once its publicly ready, and in public download.
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| | Martin White
Posts 85 28 Dec 2019 17:50
| Yes, it was suggested that I should update to the one on slack. It went well enough and was easy to do - but then I have done FPGA coding before so i already know the process. I can't say that I noticed any difference in my V4SA though. But without a changelog I wouldn't know if anything was likely to change.
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