No problem I can explain you this.
Amiga is a multitasking OS.
This means you can have several programs running at same time.
And in addition to this you can have drivers or other code reacting on Interrupts.

The Registers of the CPU are used by all programs.

Lets make an example.
Lets say you have an code triggered by an IRQ.
This handler now saves some registers with movem.l D0-D7..
This means the 32bit portion of the register are saved and later again stored. All very normal.

When the program now executed MOVEQ - then this instruction should update the lower 32bit of the register - AND is not allowed to touch the high bits. As the program did also not save them.

This means the behavior of the CPU is not allowed to change.
And registers outside of the saved - are not allowed to be trashed.

You see what I mean? I think its simple to understand.

VALUE     = Instruction used   = Instruction Length IN Byte
  0        = CLR.l (A0)         =  2 byte
  -1       = MOV3.l #-1,(A0)    =  2 byte
  +1       = MOV3.l #1,(A0)     =  2 byte
  4000     = MOVI.L #4000,(A0)  =  4 byte
  -4000    = MOVI.L #-4000,(A0) =  4 byte
  and of course the "normal" instruction
             MOVE.L #imm,(A0)   =  6 byte   

What do you think?

Do you know how many instruction Bytes for example PowerPC needs to do the same?

               POWERPC                   APOLLO 68080 
  -1             2 instruction, 8 BYTE     1 instruction, 2 BYTE
   1            2 instruction, 8 BYTE     1 instruction, 2 BYTE
  4000           2 instruction, 8 BYTE     1 instruction, 4 BYTE
  1.000.000.000  3 instruction, 12 BYTE    1 instruction, 6 BYTE
  
  
  setting a 32bit value in memory NOT pointed to by register to a value
  
               POWERPC                   APOLLO 68080
  -1             3 instruction, 12 BYTE     1 instruction, 6 BYTE
   1            3 instruction, 12 BYTE     1 instruction, 6 BYTE
  4000           3 instruction, 12 BYTE     1 instruction, 8 BYTE
  1.000.000.000  4 instruction, 16 BYTE     1 instruction, 10 BYTE
  

void memclr (int length, int * ptr)
{
  for(;length--;){
    *ptr++= 0;
    *ptr++= 0;
    *ptr++= 0;
    *ptr++= 0;
   }
}

Compiled with -m68080 -O2 -fomit-frame-pointer

_memclr:
         move.l (8,sp),a0
         move.l (4,sp),d0
         jra .L2
.L3:
         clr.q (a0)+
         clr.q (a0)+
.L2:
         dbral d0,.L3
         rts

I think this is very nice now.
What do you think?

memclr:
          bra .L2
.L3:
          clr.q (a0)+
          clr.q (a0)+
.L2:
          dbral d0,.L3
          rts

  void memclr (int length, int * ptr)
  {
   for(;length--;){
     *ptr++= 0;
     *ptr++= 0;
     *ptr++= 0;
     *ptr++= 0;
    }
  }
  

  _memclr:
          move.l (8,sp),a0
          move.l (4,sp),d0
          jra .L2
  .L3:
          clr.q (a0)+
          clr.q (a0)+
  .L2:
          dbral d0,.L3
          rts
  

I see one more possible improvement:

  _memclr:
          move2.l (4,sp),D0:A0
          bra .L2
  .L3:
          clr.q (a0)+
          clr.q (a0)+
  .L2:
          dbral d0,.L3
          rts
  

Yes, but for 32 bits coding, higher longword (high 32 bits) is totally unused. Then is not important if this 0 or -1 via moveq. I dont see/know 32 bits 68k instruction which can be problematic. Unused for me is equal can be ignored.

But for 64 bits coding, 64 bits moveq can be really powerful. Much powerful for me like clr.q, f.e

moveq #0,D0 ; 64 bits
moveq #-1,D1 ; 64 bits
movem.q D0-D1,(A0)+

or
  moveq #-1,D0
  clr.l D0
we have $FFFFFFFF00000000 64 value in only 4 bytes.

The CPU in an Amiga is used by the Operating system,
and the Amiga can run multible programs at the same time.
We call this multitasking.
How does this work that programs run at the same time on one CPU?
 
This works like this:
1)
The CPU executes instructions of the current program.
One instruction after the other .. And the program uses the registers of the CPU.

If a running  program is a 32bit program then it might only use the 32bit lower part of all the registers. If the program is doing 64bit operations then it will use the full registers all 64bits.
 

Lets say you run a new program using 64bit.
For example RIVA the video player.
RIVA uses a lot 64bit operations.
 
Lets say while you play video...the Super-AGA network chip receives a new packet, the Super-AGA chip will DMA this packet (for free) to the memory, and when done it will throw an IRQ to signal the network software driver that a new packet was received.
 
The software driver will be called to process it.
This is called "Interrupt"..
The software driver might be 32bit code..
It will use MOVEM.L to saved the content of the register... do some work.. maybe send a signal to a task e.g. tell the Webbrowser that a packet for it was received... and then it will restore the registers again and "RTE" will return from the exception.
So that the CPU will continue to execute the where it was before.
 
In this case it will continue to run RIVA the video player.
 
All this is done very fast, the user will not notice this quick interrupt switch. I hope my example was easy to follow?
 
Important to understand is that the 32bit interrupt code has saved the 32bit part of the register that it uses...
And the 32bit task with its instruction that it uses ... its also only allowed to touch the lower 32bit part.
 
This is very important.
As otherwise the 32bit code would accidentally trash the high part of the register - which would crash RIVA - as the high parts were never saved and never restored.
 

So yes it makes a lot sense that MOVEQ behaves for 32bit programs exactly as always worked - touching 32bit.

GCC now support MOVE2.L !!