Overview Features Coding Performance Forum Downloads Products OrderV4 Contact

Welcome to the Apollo Forum

This forum is for people interested in the APOLLO CPU.
Please read the forum usage manual.



All TopicsNewsPerformanceGamesDemosApolloVampireAROSWorkbenchATARIReleases
Information about the Apollo CPU and FPU.

Apollo Core As Real CPU?

Master APEX

Posts 44
04 Jul 2020 21:45


Here we go:
EXTERNAL LINK 
Interesting. Should Apollo enter the competition?


Eric Gus

Posts 459
05 Jul 2020 03:10


Apollo core isnt opensource.


Adam A

Posts 125
05 Jul 2020 08:04


The idea could still be great for other open-source projects but 130nm !? thats too old


Smartroad 78

Posts 116
05 Jul 2020 16:55


"The idea could still be great for other open-source projects but 130nm !? thats too old"

It's around P4 territory and they were reaching 2GHz or so. I mean temperature wise they weren't that far off of the suns surface, but still. Would be interesting to see the 68080 at that sort of speed given the 68060 was 600nm!!


Tim Waite

Posts 32
05 Jul 2020 22:35


Unless the SAGA/AGA was removed and it was purely a CPU, this would be a system on a chip type design.  Very interesting.  Might get some non-amiga uses. 


Gunnar von Boehn
(Apollo Team Member)
Posts 5730
09 Jul 2020 10:42


We will discuss the option with them.
But that this makes probably no that much sense this year - should be obvious to anyone.
   
Compiling VHDL into an ASIC is a complex process and requires a lot of time and effort to be done "properly".
   
If you want to do this right then this effort allows for a lot of tuning and tweaking - its not just a "push button" process.
Real companies like INTEL have teams of 500 people tuning the ASIC run for about 12-24 month.
So if you want to do it "proper" then this needs a lot of time and preparation.
   
The Vampire is right now in a exiting phase with constant improvements and adding of new AGA features.
   
Making an ASIC runs could make sense after all this is done and fully finished.
Making today an "hip-shot" push button run - makes much less sense - as obviously by the time the 100 chips come from factory the core is "outdated" and with a hip-shot the performance gain is not impressive anyway.
 


Richard Gatineau

Posts 58
14 Jul 2020 15:44


Now, we know that never an ASIC version of the 68080 will be expected in the future, if it require so many peoples/time to do that.


Roy Gillotti

Posts 494
14 Jul 2020 18:25


Richard Gatineau wrote:

Now, we know that never an ASIC version of the 68080 will be expected in the future, if it require so many peoples/time to do that.

That isn't what he was implying.

There are specialized design groups in the industry that could be hired for the work, then it's just a matter of money needed.


Gunnar von Boehn
(Apollo Team Member)
Posts 5730
14 Jul 2020 20:35


Richard Gatineau wrote:

Now, we know that never an ASIC version of the 68080

 
Could it be that you misunderstood what I said?
The point that I tried to make is very simple.
 
I believe that if you do an ASIC, then it makes sense to take time and to do it right.
I'm not a fan of bad solutions.
As you might know we did spend 12 years of serious developing of the 68080 CPU.
If you spend that much time to develop a good CPU, then in my opinion it also makes good sense to not spoil it with a hasty, rushed ASIC run.
 
As you can imagine yourself, a hipshot / hasty rush will obviously  results in a non optimal results.
To me it makes good sense to take time and make a good ASIC tuning.
This job can take 12 month or more.




Peeri the Sunlight

Posts 64
16 Jul 2020 21:46


Disclaimer: This is just writing some one who don't know anything about chip making process!

If we think about tuning 68080 to ASIC, is it possible to build in "small" matrix of FPGA inside the the asic?
Meaning that if there is need for non time critical improvements later on, the possibilities to improve and add features to core still exists. And if needed "lite" version of chip where some features disabled, it can be programmed by apollo team. (and if possible add small sdram buffer for very resident viruses etc. which can sneak to the cores fpga. :/ )
This might improve chip life span, and make possible to fix if there is some bug without making new masks.

posts 10