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Information about the Apollo CPU and FPU.

Missing Opcodes Informtaion

Kamelito Loveless

Posts 57
02 Jul 2019 13:23


Hi,
  Not sure if it is normal but the opcodes below do not have details informations but give a 404 error (Instructions link)
 
  RTE
  RESET
  STOP
  MOVE to USP
  MOVE from USP
  FRESTORE
  FSAVE
  FMOVE
  FADD
  FSUB
  FABS
  FNEG
  FMUL
  FDIV
  PSUB
  PSUBUS
  PADDUS
  ([dis,An],Xn*Scale,dis)

Ps is there documentation about the SAGA registers, something like the HRM?


Philippe Flype
(Apollo Team Member)
Posts 257
02 Jul 2019 19:51


Hi Kamelito

There is no best documentation than the original Motorola ones.

The AC68080 use the same basis than the MC680x0, so i strongely advise anyone who wants code
for the AC68080 to first masters the legacy programmer manual, still hosted by NXP here :

EXTERNAL LINK 

You will find there all the CPU instructions from MC68000 to MC68060,
and so 95% of the integer instructions set of the 080.

Also, inside are the FPU instructions from the MC68881/68882 to the MC68060,
and so 100% of the floating-point instructions of the 080.

Clearly, the AC68080 is the most compatible 68000 processor, so all needed is there, as a first shoot.
Every experienced 68K coders all use them instead of any other documentation, such as democoders.

Additionally, i can advise the reading of the MC68060 manual documentation.
There is many to learn about some specific registers and how best code for SuperScalar, for example.
The AC68080 applies a lot of those concepts, so all here remains true and is solid base for pushing
the motorola to its best.

EXTERNAL LINK 

For the specific instructions of the AC68080, there is the official AMMX documentation.

CLICK HERE 

You can code them directely with VASM by Frank Wille
or any assembler with some DC.W opcode, like i do sometimes in Devpac.

EXTERNAL LINK 

@Ps is there documentation about the SAGA registers, something like the HRM?

About the SAGA registers, there are stuff explained in the official Wiki page.
Still there is some updates needed, though.

EXTERNAL LINK 




Kamelito Loveless

Posts 57
02 Jul 2019 20:46


Hi Flype,
I knew about the Motorola manuals but didnít  knew about the wiki thanks.
I have done 68000  coding long ago mostly patches.
 


Philippe Flype
(Apollo Team Member)
Posts 257
02 Jul 2019 21:12


I guess those links can be useful to anyone who reads that thread :)


Kamelito Loveless

Posts 57
02 Jul 2019 21:22


Yep of course :)


Stefan "Bebbo" Franke

Posts 126
03 Jul 2019 10:13


Philippe Flype wrote:

  For the specific instructions of the AC68080, there is the official AMMX documentation.
 
  CLICK HERE 

how do you code these moves?


    move.l a0,b0
    move.l b1,a1
    move.l a2,e2
    move.l e3,e11
    move.l e20,d4




Gunnar von Boehn
(Apollo Team Member)
Posts 4169
03 Jul 2019 10:57


Stefan "Bebbo" Franke wrote:

Philippe Flype wrote:

  For the specific instructions of the AC68080, there is the official AMMX documentation.
 
  CLICK HERE   
 

 
  how do you code these moves?
 
 

      move.l a0,b0
      move.l b1,a1
      move.l a2,e2
      move.l e3,e11
      move.l e20,d4
 

 

APOLLO Register look like this

ADDRESS-REGS
  A0-A7
  B0-B7 

DATA-REGS
  D0-D7
  E0-E7
  E8-E15
  E16-E23

FPU-REGS
  F0-F7
  E0-E7
  E8-E15
  E16-E23

This means
  - for EA calculation 16 Address regs are available
  - for DATA-ALU Operations 32 Regs can be used.
  - for FPU Operations 32 Regs can be used.

FPU and ALU share some registers.
This is an optimization to keep context switch overhead low.

By putting a prefix opcode called "BANK" in front of a normal integer or FPU instruction these extra register can be used.


Stefan "Bebbo" Franke

Posts 126
03 Jul 2019 14:52


Gunnar von Boehn wrote:

  ...
    By putting a prefix opcode called "BANK" in front of a normal integer or FPU instruction these extra register can be used.
 

 
  That's what is in the referenced doc:
 
 

  BANK    MACRO
          ;        ----CCC-DDCCAABB  AA        BB    DD
          dc.w    (%0111000100000000+((\1)*%100)+(\2)+((\3)*%1000000))
          ENDM
 

 
 
  so
 

      BANK 1,2,0
      move.l d0,d1
 

  is a
 

      move.l e0,e9
 

  ?
 
  How do you encode
 

      move.l (b0,e8*4,123),e16
 

  ??
 
 


Gunnar von Boehn
(Apollo Team Member)
Posts 4169
03 Jul 2019 19:51


Stefan "Bebbo" Franke wrote:

  How do you encode

68k always has register banks of 8.
8 Addres, 8 Data.

APOLLO provides 2 BANKS of ADDRESS, and 4 BANKS of DATA/FPU Regs.
The BANK instruction does extend the 2 Operants by 2 bits.
In case of FPU regs the 2 bits allow to access all 4 Banks=32 Regs
In case of DATA resgs the 2 bits allow to access all 4 Banks=32 Regs
In case of EA, the 2 bits are split in two times 1.
The first allows to use all 16 ADDR regs.
The second allows to select as INDEX from (A0-A15 and D0-D15).

I will make some pictures to explain this better.


Stefan "Bebbo" Franke

Posts 126
03 Jul 2019 21:39


RANK 3,3
    move.l 16(a0, d1*4),d2
 
  is
 
    move.l 16(a8, d9*4),e18
 
  which is the same as
 
    move.l 16(b0, e1*4),e18
 
  thus e16-e32 can't be used as index reg.


Gunnar von Boehn
(Apollo Team Member)
Posts 4169
03 Jul 2019 22:02


Stefan "Bebbo" Franke wrote:

  RANK 3,3
      move.l 16(a0, d1*4),d2
   
    is
   
      move.l 16(a8, d9*4),e18
   
    which is the same as
   
      move.l 16(b0, e1*4),e18
   
    thus e16-e32 can't be used as index reg.

As INDEX you can select from (A0-A15 and D0-D15).
This gives 32 regs possible as INDEX.



Gunnar von Boehn
(Apollo Team Member)
Posts 4169
04 Jul 2019 10:20


Hallo Bebbo,
 
Lets talk about BANK.
 
BANK is the new pre-fix word.
On 68K all registers are in "BANKS" of 8 Registers.
We have 2 BANKS of ADDR Regs (A0-A7,B0-B7)
and 4 BANKs of DATA Regs (D0-D7,E0-E7,E8-E15,E16-E23)
The FPU can also access 32 regs (F0-F7,E0-E7,E8-E15,E16-E23)
The overlap of extended Data and FPU regs is on purpose.

The encoding of BANK looks like this:

 
OK what can we do with BANK?

68K Instructions are 2 OPP.
ADD.L D0,D1
(A)(A) will allow extend the BANK for Operant A.
So to say the high bits of the register address.
(B)(B) will allow extend the BANK for Operant B.
Again the high bits.

(C)(C) is a special trick and allows to change the DESTINATION of the instruction.
This means with Bank you can create this:

FADD F0+F1 -> F2



Stefan "Bebbo" Franke

Posts 126
15 Jul 2019 07:48


Gunnar von Boehn wrote:

  APOLLO Register look like this
 
 
  ADDRESS-REGS
  A0-A7
  B0-B7 
 
  DATA-REGS
  D0-D7
  E0-E7
  E8-E15
  E16-E23
 
  FPU-REGS
  F0-F7
  E0-E7
  E8-E15
  E16-E23
 

 
  This means
  - for EA calculation 16 Address regs are available
  - for DATA-ALU Operations 32 Regs can be used.
  - for FPU Operations 32 Regs can be used.
 
  FPU and ALU share some registers.
  This is an optimization to keep context switch overhead low.
 
  By putting a prefix opcode called "BANK" in front of a normal integer or FPU instruction these extra register can be used.

what value do you get in e1 / e2 after

  fmove.d #0x3ff0000000000000,e0
  move.l  e0,e1
  move.q  e0,e2

(move.q means 64 bit move)



Gunnar von Boehn
(Apollo Team Member)
Posts 4169
15 Jul 2019 07:57


Stefan "Bebbo" Franke wrote:

  what value do you get in e1 / e2 after
 
    fmove.d #0x3ff0000000000000,e0
    move.l  e0,e1
    move.q  e0,e2
 
  (move.q means 64 bit move)

MOVE.B will copy the lower 8bit (7..0) and leave the bits 63...8  unchanged
MOVE.W will copy the lower 16bit (15..0) and leave the bits 63...16  unchanged
MOVE.L will copy the lower 32bit (31..0) and leave the bits 63...32  unchanged

MOVE.Q will copy the whole register.



Stefan "Bebbo" Franke

Posts 126
15 Jul 2019 10:27


Gunnar von Boehn wrote:

Stefan "Bebbo" Franke wrote:

  what value do you get in e1 / e2 after
 
    fmove.d #0x3ff0000000000000,e0
    move.l  e0,e1
    move.q  e0,e2
 
  (move.q means 64 bit move)
 

  MOVE.B will copy the lower 8bit (7..0) and leave the bits 63...8  unchanged
  MOVE.W will copy the lower 16bit (15..0) and leave the bits 63...16  unchanged
  MOVE.L will copy the lower 32bit (31..0) and leave the bits 63...32  unchanged
 
  MOVE.Q will copy the whole register.
 

does it contain the IEEE floating point format if accessed as data register? Or something else?




Gunnar von Boehn
(Apollo Team Member)
Posts 4169
15 Jul 2019 11:06


Stefan "Bebbo" Franke wrote:

 
Gunnar von Boehn wrote:

 
    MOVE.Q will copy the whole register.
   
 

 
  does it contain the IEEE floating point format if accessed as data register? Or something else?
 

 
The copied content will stay the same. Bit by bit.
From an FPU point of view the value stays the same.

More info:
APOLLO 68080 has 64bit registers.

Float-Double is hold in register as it.
Float-Single is on load "FMOVE.S (mem),F0" converted to double
Float-Extended is on load "FMOVE.X (mem),F0" converted to double
FMOVEM stores and saves in extended format for compatibility.

The registers can be used for integer or floating point likewise.
This means you can do a memcopy also with FMOVE.d instructions.
And Floating registers can also be back-uped with integer MOVE.
 
 
 

posts 16